1. Field of the Invention
The present invention relates to a semiconductor integrated circuit in which spare flip-flops are contained beforehand as repair cells.
2. Related Art
With a rapid expansion of the market of products that carry semiconductor integrated circuits in recent years, the semiconductor integrated circuit products are increasingly diversified and sophisticated and their life cycles are shortening. Under such circumstances, short-term development and high functionality are required of semiconductor integrated circuits.
Also, as semiconductor manufacturing technologies progress, a large-scale circuit previously uncontainable in a single semiconductor integrated circuit chip can now be implemented in a single semiconductor integrated circuit chip through microfabrication.
This creates a demand for semiconductor integrated circuit design techniques that enable an enormous size of circuit to be packed on a single semiconductor integrated circuit chip in a short time.
The use of a most advanced microfabrication technique in semiconductor integrated circuit design has advantages such as reducing a total semiconductor cost in a product system and allowing a large-scale circuit to be packed on a single semiconductor integrated circuit chip, but also has disadvantages such as a longer diffusion period, a higher mask price, greater difficulty in timing design for signal integrity, and a longer functional inspection period.
In view of this, the following method is conventionally used to develop a high-performance large-scale semiconductor integrated circuit in a short time. In addition to logic circuits that achieve a predetermined function, logic circuits for functional changes are placed beforehand in a semiconductor integrated circuit as repair cells, so that a functional change can be easily made in a short time by changing a wiring layer after placement of an order for masks for composing transistors.
Japanese Patent Application Publication No. 2000-150659 discloses one example of layout design method that uses repair cells.
According to this method, in an initial circuit design stage, spare standard cells for circuit changes are inserted in a layout in anticipation of circuit changes which may later become necessary, so that a circuit change can be made to remove a timing constraint violation or the like found after layout design or manufacture of a semiconductor integrated circuit. This being so, when a circuit change becomes necessary, the change can be made by using only a repair standard cell and wiring.
According to this conventional technique, the spare standard cells are placed beforehand, so that a circuit change can be made by using only a spare standard cell and wiring. However, to supply a clock signal to the spare standard cell used for the circuit change, it is necessary to form a new wire for supplying the clock signal to the spare standard cell. This may disturb the balance in timing adjustment of the clock signal supplied to main standard cells used for achieving the original function of the semiconductor integrated circuit. Also, crosstalk may occur between the new wire and its neighboring signal line, which can further disturb the balance in timing adjustment of the clock signal.
Due to these problems, it is difficult to perform a circuit change without disturbing synchronization. This makes it impossible to reduce a design time.